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Board Control and Status Register - BCSR
5.11.1 BCSR0 Board Control—Status Register 0
The BCSR0 is a control register on the MPC8272ADS. It is accessed at offset 0 from BCSR
base address. It may be read or written at any time 1 . BCSR0 gets its defaults upon
Power-On reset. BCSR0 fields are described in Table 5-7.
Table 5-7. BCSR0 Description
BIT
0-5
6
7
8 - 31
MNEMONIC
Reserved
GPL LED 1
GPL LED 2
Reserved
Function
S
General Purpose Led 1. General purpose Led to be used by the user.
General Purpose Led 2. General purpose Led to be used by the user.
Un-implemented
PON
DEF
0
0
0
0
ATT.
R/W
R,W
R,W
R
5.11.2 BCSR1 Board Control—Status Register 1
The BCSR1 is a control register on the MPC8272ADS. It is accessed at offset 4 from BCSR
base address. It may be read or written at any time 2 . BCSR1 gets its defaults upon
Power-On reset. The fields are described in Table 5-8
Table 5-8. BCSR1 Description
BIT
0
MNEMONIC
Conf_Word
Function
Config_Source . When asserted ( low ) Hard Reset Configuration Word is
PON
DEF
0
ATT.
R
sourced from the BCSR. When negated, Hard Reset Configuration Word is
sourced from the FLASH/EEPROM. The assignments selection is done via
a dedicated jumper JP7.
1
FLASH_CS0
FLASH CS0 . When asserted ( low ) CS0 is assigned to the FLASH SIMM
0
R
and CS4 is assigned to E 2 PROM. When negated, CS0 is assigned to the
E 2 PROM and CS4 is assigned to the FLASH SIMM. The assignments
selection is done via a dedicated jumper.
2
ATM_EN
ATM Port Enable . When asserted ( low ) the ATM UNI chip (PM5384)
1
R,W
connected to FCC1 is enabled for transmission and reception. When
negated, the ATM transceiver is in standby mode, freeing all its i/f signals for
off-board use via the expansion connectors.
3
ATM_RST
ATM Port Reset . When asserted ( low ), the ATM port transceiver is in reset
1
R,W
state. This line is driven also by HRESET signal of the MPC8272.
1 Provided
2 Provided
that BCSR is not disabled.
that BCSR is not disabled.
Chapter 5. Module Design
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